Using the ESP8266 WiFi Transceiver module with a 5v Arduino requires the use of level shifting circuitry. A resistor divider (1k and 2k typically) works perfectly well for signals from the 5v Arduino to the ESP8266 3.3v. However, while many people connect 3.3v derived signals directly to a 5v powered input, to maintain good noise margins requires an active interface. While there are several bus drivers available that will perform level translation and buffering (such as the 74LVC245A), they are overfill when just a couple of signals are involved.
In the design of the ESP8266 WiFi Module: Data Logger there are just two signals (TX and RX) that require level shifting and this circuit, using a couple of 2N7000 N-Channel Enhancement Mode Field Effect Transistors is small and works very well.
Level Shifting Interface
Now, I recognize that some of you may not be convinced that this actually works. Unfortunately this may be because I failed to draw in the drain-substrate diode of the MOS-FET (see state 3 below).
Operation of the level shifter:
The following three states should be considered during the operation of the level shifter:
- No device is pulling down the bus line. The bus line of the ‘lower-voltage’ section is pulled up by its pull-up resistors to 3.3V. The gate and the source of the MOS-FET are both at 3.3V, so its VGS is below the threshold voltage and the MOS-FET is not conducting. This allows the bus line at the ‘higher-voltage’ section to be pulled up by its pull-up resistor to 5V. So the bus lines of both sections are HIGH, but at a different voltage level.
- A 3.3V device pulls down the bus line to a LOW level. The source of the MOS-FET also becomes LOW, while the gate stays at 3.3V. VGS rises above the threshold and the MOS-FET starts to conduct. The bus line of the ‘higher-voltage’ section is then also pulled down to a LOW level by the 3.3V device via the conducting MOS-FET. So the bus lines of both sections go LOW to the same voltage level.
- A 5V device pulls down the bus line to a LOW level. The drain-substrate diode of the MOS-FET means that the ‘lower-voltage’ section is pulled down until VGS passes the threshold and the MOS-FET starts to conduct. The bus line of the ‘lower-voltage’ section is then further pulled down to a LOW level by the 5V device via the conducting MOS-FET. So the bus lines of both sections go LOW to the same voltage level.
To illustrate, I used the 32kHz square-wave signal from an RTC module. In the first instance, the RTC module was powered by 5v and in the second by 3.3v. The following screen capture from my oscilloscope shows the RTC 32KHz 5V signal (green) shifted to 3.3V (yellow). The on-screen measurements show the shift from 3.9V peak-to-peak (0.6 – 4.5V) to 2.9V peak-to-peak (0.4 – 3.3V). Just what we wanted!
Level shifting from 5v to 3.3v. Notice the peak-to-peak measurements for each channel (green – input, yellow – output)
Now, when the RTC is powered from 3.3V the square wave has 2.9V peak-to-peak (0.6 – 3.3V). The trace below shows the shift to 3.3V peak-to-peak (0.5 – 3.8V). For a typical CMOS gate operating at 5V, the acceptable input signal voltages range from 0 – 1.5V for a logic 0 state, and 3.5 – 5V for a logic 1 state. While several designs suggest a direct connection between a 3.3V output and 5V input is okay, if it works at all there is absolutely no noise margin as a 3.3V output is lower than the nominal minimal input voltage level for a logic 1 state.
However, level shifting from 3.3V outputs to 5V inputs using this design provides at least 0.3V of noise margin.
Level shifting from 3.3v to 5v.
Hope that this helps…